1. Field Of the Invention
This invention relates generally to programmable logic arrays, and particularly to a programmable logic array that includes flash memory cells.
2. Description of the Related Art
Programmable logic devices (PLDs) are well-known programmable integrated circuits that may be used to replace discrete logic components. PLDs employ a number of competing architectures, all of which have evolved from the basic AND/OR plane architecture. (A species of the basic AND/OR plane architecture is described below in connection with FIG. 2a.)
Numerous types of memory elements may be used in PLD architectures to provide programmability. One such memory cell, known as a flash memory cell, is both electrically erasable and programmable. A basic flash memory cell 100 is shown in FIG. 1a.
Flash memory cell 100 includes an access transistor 110 and a double-polysilicon storage transistor 120. Storage transistor 120 has a floating polysilicon gate 122 that is isolated in silicon dioxide and capacitively coupled to a polysilicon control gate 124. Storage transistor 120 also has a region of silicon dioxide between the floating gate 122 and a drain 126 that is thin enough to permit electrons to tunnel to and from floating gate 122 when the proper bias voltages are applied to the terminals of storage transistor 120. The region of silicon dioxide is conventionally known as the "tunnel oxide."
As shown in FIG. 1a, storage transistor 120 is programmed by grounding its source 128, applying approximately 5 to 6 volts to its drain 126, and connecting its control gate 124 to a programming voltage V.sub.PP that is high relative to the operating voltage V.sub.CC. Typical values of the programming voltage V.sub.PP and operating voltage V.sub.CC are 12 volts and 5 volts, respectively. With storage transistor 120 thus biased, electrons travel through the tunnel oxide to the floating gate 122, leaving the floating gate 122 with a net negative charge. This net negative charge shifts the threshold voltage V.sub.t (i.e., the voltage at which an MOS transistor begins to conduct) of storage transistor 120 in the positive direction to a voltage that is greater than V.sub.CC.
As shown in FIG. 1b, storage transistor 120 is erased by grounding control gate 124 and applying a relatively high voltage (e.g., 12 volts) to the source 128. This bias allows electrons to tunnel away from the floating gate 122 through the tunnel oxide to be swept away by the large positive voltage on the source 128. The loss of electrons (i.e., the loss of negative charge) on floating gate 122 shifts the threshold voltage V.sub.t of storage transistor 120 in the negative direction to a voltage that is less than V.sub.CC.
When erasing storage transistor 120, it is possible to remove too many electrons from floating gate 122, resulting in excess positive charge on floating gate 122. This condition is commonly known as "over-erase." Access transistor 110 is provided to prevent storage transistor 120, in the event that storage transistor 120 is over-erased, from conducting as a result of excess positive charge on floating gate 122.
When the PLD operates as a logic device, each of the storage transistors (e.g., storage transistor 120) has V.sub.CC applied to its control gate 124. The state of each storage transistor may then be "read" by determining whether the storage transistor conducts. If the storage transistor is programmed, V.sub.CC is less than the threshold voltage V.sub.t so the storage transistor will not conduct. If, on the other hand, the storage transistor is erased, V.sub.CC will be sufficient to turn the storage transistor on.
After flash memory cell 100 is programmed or erased, a test is generally performed to verify the state of storage transistor 120. For example, to verify that storage transistor 120 is properly programmed, a verify-program voltage V.sub.VP is applied to the control gate 124 to determine whether the threshold voltage V.sub.t of storage transistor 120 is sufficiently high to keep storage transistor 120 from conducting when V.sub.CC is applied to the control gate 124. The verify-program voltage V.sub.VP applied to the control gate 124 is greater than V.sub.CC by a safety factor of, for example, 3 volts. This safety factor allows for noise and for a possible negative shift of the threshold voltage V.sub.t caused by electrons escaping from the floating gate 122 over the life of memory cell 100.
As shown in FIG. 1c, when the programmed or erased state of storage transistor 120 is verified, V.sub.CC is applied to the control gate of access transistor 110 to turn access transistor 110 on. A sense amplifier 150, coupled across the series connected access transistor 110 and storage transistor 120, determines whether storage transistor 120 conducts. If the threshold voltage V.sub.t of storage transistor 120 is sufficiently high, over 8 volts for example, a verify-program voltage V.sub.VP of 8 volts will not turn storage transistor 120 on. As a result, verify sense amplifier 150 will not sense current through the series coupled transistors 110 and 120.
When storage transistor 120 is erased, the state of erasure may be verified by ensuring that storage transistor 120 conducts with V.sub.CC applied to control gate 124. To allow for noise, a verify-erase voltage V.sub.VE less than V.sub.CC by a safety factor of, for example, 3 volts is applied to control gate 124 of storage transistor 120. V.sub.CC is then applied to the control gate of access transistor 110 to allow sense amplifier 150 to access storage transistor 120. If storage transistor 120 is properly erased, verify sense amplifier 150 will detect a current through series transistors 110 and 120 with the two-volt verify-erase voltage V.sub.VE applied to the control gate 124 and V.sub.CC applied to the control gate of access transistor 110.
FIG. 2a illustrates a simple 2-input AND/OR array 200 using flash memory cells. AND/OR array 200 and its associated description provide a basic understanding of AND/OR arrays in general. AND/OR array 200 does not represent a functional circuit, and is not admitted prior art.
Array 200 includes eight flash memory cells similar to flash memory cell 100 of FIGS. 1a through 1c. For example, access transistor 202A and storage transistor 204A make up one such cell. Access transistor 202A receives an input A from an access wordline AWL.sub.A, and access transistor 202.sup.A receives the complement of signal A (.sup.A) through an inverter 206A.
When AND/OR array 200 is operating as a logic device (i.e., in the "logic mode"), the input voltage on the control gates of all of the storage transistors, for example transistors 204A and 204.sup.A, is V.sub.CC. As discussed above with respect to FIG. 1, a programmed storage transistor will not conduct with V.sub.CC applied to its control gate, whereas an erased storage transistor will. Thus, when AND/OR array 200 operates as a logic device, each programmed storage transistor is effectively an open circuit and each erased storage transistor is effectively a short circuit.
When either of the inputs A or B turns an access transistor on that is connected in series with an erased storage transistor, the sense amplifier coupled across those transistors will sense a current through the series connected transistors and output a low voltage (logic zero) on a corresponding bit line BL. For example, assuming storage transistor 204A is erased, a 5-volt signal on input A will turn access transistor 202A on, creating a current path through series transistors 202A and 204A. Sense amplifier 208 will sense the current through these series coupled transistors and output a low voltage (typically zero volts) on bit line BL.sub.1.
Bit lines BL.sub.1 and BL.sub.2 are connected to an OR gate 220 that outputs, on an output node Y, an OR function of the signals on bit lines BL.sub.1 and BL.sub.2.
AND/OR array 200 can be programmed to provide at node Y any logic function of the inputs A and B. For example, FIG. 2b shows a conventional exclusive OR gate with inputs A and B, and an output Y. FIG. 2b shows the truth table for the exclusive 0R gate and its associated boolean equation. The following example shows how AND/OR array 200 may be programmed to provide an exclusive-OR function of inputs A and B at output node Y.
To program AND/OR array 200, the transistors associated with sense amplifier 208 are programmed to output a logic one, typically 5 volts, when the product term A.sup.B of the boolean equation is true. To accomplish this, storage transistors 204A and 204.sup.B are programmed. The other product term, .sup.A B, is simulated using the access and storage transistors associated with sense amplifier 216. To accomplish this simulation, storage transistors 212.sup.A and 212B are programmed.
Recalling that a programmed transistor does not conduct with 5 volts applied to its control gate, AND/OR array 200 programmed to act as an exclusive OR gate can be represented by the AND/OR array of FIG. 2c, where programmed storage transistors are shown as open circuits.
AND/OR array 200, as shown programmed in FIG. 2c, operates as an exclusive OR gate as follows:
If input A is a logic zero, then the signal .sup.A from inverter 206A is a logic one. A logic one on the control gate of access transistor 202.sup.A will cause access transistor 202.sup.A to conduct. Because storage transistor 204 is erased, it too will conduct. Therefore, the series connected transistors 202A and 204.sup.A will provide a path for current. Sense amplifier 208 will sense this current and output a logic zero on bit line BL.sub.1 to OR gate 220. The logic zero on input A will also be fed via access wordline AWL.sub.A to the transistors associated with sense amplifier 216. Access transistor 210A will not conduct with the logic zero on its control gate, and access transistor 210.sup.A will not conduct because storage transistor 212.sup.A is programmed to act as an open circuit. However, the logic zero input on input B is inverted by inverter 214B, so that a logic one is supplied on terminal B to the control gate of access transistor 210.sup.B. Access transistor 210.sup.B, thus turned on, will provide a current path through erased storage transistor 212.sup.B. Sense amplifier 216 will sense this current and output a logic zero on bit line BL.sub.2. OR gate 220, having a logic zero at each input, will output a logic zero at output Y. Referring back to the truth table of FIG. 2b, the logic zero output is correct when two zeros are input to an exclusive-0R function.
Moving on to the second line of the truth table, when input A is a zero, a logic one on the gate of access transistor 202.sup.A will cause current to pass through erased storage transistor 204.sup.A. This current will be sensed by sense amplifier 208, which will consequently output a logic zero on bit line BL.sub.1 to OR gate 220. A logic one on input B will turn access transistor 210B on, which will fail to conduct because of the nonconducting path provided by storage transistor 212B. The inverted logic one (i.e., logic zero) at signal .sup.B will be provided to access transistor 210.sup.B, which will consequently not conduct. Sense amplifier 216, having no current path to sense, will output a logic one on bit line BL.sub.2 to OR gate 220. OR gate 220, having a logic one on one input, will output a logic one on output node Y. Thus, the second line of the truth table of FIG. 2b is satisfied.
In the third line of the truth table of FIG. 2b, input A is a logic 1 and input B is a logic zero. In this case, access transistor 202A cannot conduct because storage transistor 204A is effectively open, and access transistor 202.sup.A does not conduct because it is turned off. Furthermore, access transistor 202B does not conduct because it is biased off and access transistor 202.sup.B cannot conduct because storage transistor 204.sup.B is effectively an open circuit. Therefore, sense amplifier 208 will output a logic one on bit line BL.sub.1, which will cause OR gate 220 to output a logic one on node Y. Thus, the third line of the truth table satisfied.
Finally, the fourth line of the truth table of FIG. 2b requires an output of logic zero when both inputs A and B are logic ones. A logic one on access wordline AWL.sub.A turns access transistor 210A on so that sense amplifier 216 outputs a logic zero on bit line BL.sub.2 to OR gate 220. Input B, also a logic one, turns access transistor 202B on so that sense amplifier 208 outputs a logic zero on bit line BL.sub.1 to OR gate 220. OR gate 220, having two logic zero inputs, outputs a logic zero on node Y, thus completing the truth table.
Using the programming scheme described above for the exclusive-OR function, AND/OR array 200 may similarly be programmed to represent any other binary function to two inputs. In practice, AND/OR arrays are typically much larger. There may be, for example, 36 wordlines, their associated complements, and 5 bit lines. Such arrays are used to represent complex logic functions.
A number of memory cells are connected in parallel to a single wordline in a conventional PLD. That is, the control terminal of a memory cell is coupled to a number of similar control terminals through a single wordline, much like the control terminals of access transistors 202A and 210A of FIG. 2 are coupled to the same wordline AWL.sub.A. Each wordline is driven by a wordline driver.
FIG. 3 shows a wordline driver 300 used for driving a wordline in the Xilinx XC7300 family of UV-erasable, EPROM-based PLDs. Those PLDs employed UV-erasable EPROM transistors as memory cells. Wordline driver 300 is used to drive a wordline that is similar in function to wordline AWL.sub.A of FIG. 2. However, the wordline output WL of wordline driver 300 is coupled directly to the control gates of the EPROM transistors instead of to an access transistor because EPROM transistors do not require an access transistor.
Wordline driver 300 generally provides two functions. First, it drives a wordline WL with a binary wordline input signal on wordline input terminal W.sub.IN. Each wordline driver is provided with a separate signal W.sub.IN, and each of these signals may be logically combined. Second, wordline driver 300 provides the voltages necessary to program its associated memory cells. Because the UV-erasable EPROM transistors driven by wordline driver 300 are not electrically erasable, the erase voltages necessary to erase a flash memory cell are not supplied.
Wordline drivers must accommodate a number of operational modes. Examples of such modes are the program and program-verify modes described above with respect to FIG. 1.
Wordline driver 300 includes input terminals L, WLS, and WLS2. These input terminals and their associated transistors are used to select the mode in which the wordline driver 300 operates. For purposes of this illustration, it is only important to note that when the signals present on input terminals L, WLS, and WLS2 are all zero volts, transistors P321, P322, and P323 are conducting, and therefore allow the voltage V.sub.CC, typically 5 volts, to turn pass transistor N317 on. This allows the input signal on terminal W.sub.IN to pass through pass transistor N317 to a CMOS inverter 324. Inverter 324 includes transistors P307, P308, and N314. Transistors P307 and N314 form a conventional two-transistor CMOS inverter. Transistor P308 is coupled between the input and the output of the two-transistor CMOS inverter to form a conventional half-latch, which serves to restore the voltage level of the signal from input terminal W.sub.IN after it passes through pass transistor N317. Inverter 324 provides the inverted W.sub.IN signal on wordline WL. In this mode, V.sub.CC is supplied to inverter 324, transistor N315, and transistor N325 from an external power supply 350 via input terminal VPI.
In the program mode, the input signals on input terminals L and WLS2 are approximately zero volts, and the input signal on terminal WLS is approximately 5 volts. The 5 volt signal on input terminal WLS turns transistor P321 off and transistor N318 on, thereby supplying zero volts to the control gate of transistor N317. Transistor N317 therefore does not conduct, and affectively isolates inverter 324 from the input signal W.sub.IN. Also during the program mode, external power supply 350 provides a programming voltage, typically 12 volts, to input terminal VPI. The 5 volt signal on terminal WLS turns transistor N316 on, thereby pulling the input of inverter 324 toward zero volts (the signal on terminal L) and turning transistor P307 on. Transistor P307 conducts the programming voltage from terminal VPI to wordline WL.
Conventional wordline driver 300 is deficient in some respects. In addition to V.sub.CC, it requires a second external source voltage for supplying the programming voltage on terminal VPI. This is undesirable because it requires an additional power supply voltage. To circumvent similar problems, other devices use on-chip voltage generators, such as charge pumps, to generate programming voltages greater than V.sub.CC. However, such devices require a switch (e.g., a multiplexer) to select between the externally supplied V.sub.CC and the internally generated programming voltage. Because of the impedance inherent in such switches, power supply signals delivered through such switches cannot deliver the level of power that a direct connection to an external power supply can provide. Hence, these switches tend to slow the operation of wordline drivers using on-chip generators.